Gary Smith EDA Consulting in Electronic Design
Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.
-
DOWNLOAD PDF
Cadence Cuts JobsAnalysis of Cadence Cutting Another 225 Jobs
“EDA vendor Cadence Design Systems Inc. will eliminate 225 jobs—or about 5 percent of the company's workforce… Cadence said the job cuts will come primarily from resizing its worldwide field organization to current business levels, decreasing investment in the manufacturing side of design-for-manufacturing technology.”
EE Times
Analysis
There are two things. First is the 5% layoff. This is basically a sales layoff that we’ve been expecting for a few months now. That fact that is only 5%, way under some estimates, says that Cadence is recovering faster than expected.
Shutting down DFM is the other. On the surface it looks a good decision; they have little chance of catching up with Mentor or Synopsys. Look a little closer however and it brings up a problem with their long term strategy. Their biggest problem is with their back-end tools. DFM capability is becoming integrated with a majority of today’s back-end tool set. At 65nm and below routers are all DFM capable. This is where Cadence has really been losing ground. Both Mentor and Synopsys have recently been successful in outsourcing some design tool research from semiconductor vendors; Mentor specifically in DFM. Without this leading-edge DFM knowledge, it will be highly improbable that Cadence can regain the technical lead in ASIC Layout, DRC and soon Custom Layout. Those three, plus the DFM tools, make up a majority of the IC CAD market dollars ( See Figure 1).
Gary SmithTo view entire paper, download the PDF here
-
2010 Market Trends
ESL, RTL, IC CAD, PCB market share, forecast & analysis by sub-apps
Publish date: Oct 2010
-
EE Times EE Life
Lori Kate was the winner of the EE Times Caption Contest! -
EDN
ESL synthesis: tips for implementing a viable ESL-synthesis flow -
Electro IQ
Gary Smith EDA market statistics 2010: Summary -
EDN
CEO on Mentor's role in IC and system design plus test -
Printed Circuit Design
EDA Ranking Shakeup First in Years
Comments
Gary,
You are absolutely correct regarding DFM and its importance. In fact it is a critical building block to establishing a learning system that leads to profitable yield.
I will respectfully beg the industry not underestimate the Cadence executive vision or make the same mistake made in once assuming Cadence had "divested" from IC test; the opposite in fact proved true in a relatively short period of time. It was the inefficient legacies by which IC/SoC test was being approached and promoted that was divested - not the fundamentals.