Intel has made their first decision by heavily funding their Fab program. Intel’s new process development and Fab division is the heart of the company. They made their CEO decision. Now, they have to feed the Fab. You probably need to break it up Intel into three parts: Manufacturing, Microprocessor, SoC Platform.
New vendors at DAC often ask, “How do you get on the What to See @ DAC list? “How much does it cost to get on the What to See @ DAC list?” We believe “Thou shalt not be a Coin-operated Analyst!” Here is how the annual list is created.
The key to our strong research is getting to know the right people. The difficulty is getting a hold of them; they are very busy engineers. The easiest way is to know what shows they attend. The DATE technical program seemed like it was custom made for my interest and theirs.
Intel has made their first decision by heavily funding their Fab program. Intel’s new process development and Fab division is the heart of the company. They made their CEO decision. Now, they have to feed the Fab. You probably need to break it up Intel into three parts: Manufacturing, Microprocessor, SoC Platform.
New vendors at DAC often ask, “How do you get on the What to See @ DAC list? “How much does it cost to get on the What to See @ DAC list?” We believe “Thou shalt not be a Coin-operated Analyst!” Here is how the annual list is created.
The key to our strong research is getting to know the right people. The difficulty is getting a hold of them; they are very busy engineers. The easiest way is to know what shows they attend. The DATE technical program seemed like it was custom made for my interest and theirs.
Market Share: Cadence regained their number two position in the market although that battle isn’t over yet. Mentor remains the Company with their eye on the future, where Cadence’s future direction is still uncertain but building. The Market Trends Executive Summary includes an overview of this year’s Market Growth including a figure comparing ESL vs. RTL markets.
The shift to commercial Design Data Management software was reaffirmed. With designs exceeding 100+M gates, design files are requiring sophisticated Design Management software that has been specifically targeted toward IC Design. General purpose or PDM tools don’t solve the problem.
Analysis of User Wants & Needs Power Survey in 2011 and how the new ITRS Power Model allows design trade-offs between frequency and gate count.
Why Software isn’t driving today’s Hardware and how Cloud Computing isn’t affecting EDA.
17th annual write up of ‘must see’ products at the 49th DAC 2012. To post / reprint the list and/or use GSEDA logo, purchase the RV for $500. View the List for Free.
Don’t miss this conference for Design Methodologists in Monterey on April 5&6. Review of compelling agenda including: SoCs and FPGAs; Top 5 EDA problems; EDA in the Cloud; Low Power with Performance: servers, software, ASIPs and Jim Hogan keynote, and 3DICs.
This was a very interesting ASP-DAC with two main take-a-ways from the conference: Parallel Computing is really, really hard, but we can do it and Homogeneous Computing is Dead.
I believe the attempt to move our verification methodologies up into the ESL Architectural level will fail. ESL Behavioral Level is where verification should start. That will cause us to completely rethink our verification approach.
Mentor Graphics has announced that it has acquired the Flowmaster Group, a UK-based provider of computational fluid dynamics (CFD) simulation software. This isn’t the first time Mentor has reached into the mechanical world. Mentor is clearly thinking out of the box here.
The transition from 32 nm to 22nm silicon will have a major impact on the design community. You will see more and more design teams deciding to leave the IC Layout portion of the design to the experts.
Intel has made their first decision by heavily funding their Fab program. Intel’s new process development and Fab division is the heart of the company. They made their CEO decision. Now, they have to feed the Fab. You probably need to break it up Intel into three parts: Manufacturing, Microprocessor, SoC Platform.
New vendors at DAC often ask, “How do you get on the What to See @ DAC list? “How much does it cost to get on the What to See @ DAC list?” We believe “Thou shalt not be a Coin-operated Analyst!” Here is how the annual list is created.
The key to our strong research is getting to know the right people. The difficulty is getting a hold of them; they are very busy engineers. The easiest way is to know what shows they attend. The DATE technical program seemed like it was custom made for my interest and theirs.
As Mark Twain once said “The reports of my death have been greatly exaggerated”, and so goes it with DATE. The move from Nice, and before that Paris, to Grenoble was as successful as the move from Munich to Dresden. Not that I won’t miss Paris and Munich; however (read more…)
Analysis of the Synopsys/ Magma tool sets: why Synopsys bought Magma, what tool markets will be affected and how it will affect the design engineer. Complications with merging the R&D teams. Will Synopsys be able to do a better job than they did with Avanti?
Why IBM uses Transactional Memory (reliability and parallel computing) and the importance of memory architectures.
The Virtual World is decreasing the sharing of peripheral information. At IC CAD, I learned that IBM is using Transactional Memory in its Super Computer.
Dynamic Power in an SoC is controlled by two major variables; Gate Count and Frequency. Once the Power Budget is set, as in the case of mobile designs, designers must trade off these two variables. As the demand for more gates is growing designers are looking at lowering the average frequency of their designs. Microprocessor vendors that are still bragging about their Gigahertz processors are missing the point.
After we published IC CAD 2011 Market Trends report, we were informed that we had significantly underreported Atoptech. They had actually grown an amazing 187% in 2010. Includes ASIC Market Trends pie chart of vendors
Ok, I’m exaggerating; this change has been going on for weeks. It’s just that going to ARM TechCon made the change obvious. By the time you left TechCon your view, one way or another, of mainstream computing had changed significantly. Either that or you weren’t paying attention.
It’s good to grow. Growth doesn’t solve all problems but it helps. The Market Trends Executive Summary includes analysis and figures of EDA market share of major players and 5 year market forecast growth per major application.
How R&D can solve the HW cost problem through review of reuse, number and size of design blocks, engineers per block and EDA tools. EDA is Responsible for developing design tools that enable the IC design process, at a design cost that allows the ecosystem to operate at a profit?
My analysis of why NVIDIA, Samsung, STMicro and Broadcom are the top four semiconductor companies for designing chips and why.
Review of Apache aquisition by ANSYS: terms, product analyses and how the joint solutions will affect customers (EMI, thermal analysis, signal & power integrity).
A description of the origins, methodology, elements and working group practices for the ITRS cost chart.
Review of my Sunday night talk, keynotes, Word on the Street from engineers about Mentor, Magma, Apache, Cadence and Synopsys. Who’s up and who’s not? Includes ITRS Cost Chart from Sunday Night talk.
The increase use of IP has driven the need for sophisticated Design Management tools. This Industry Note looks at an user survey and need for Design Management tools in the SoC and IC Design process.
16th annual list of ‘must see’ products at the 48th DAC 2011. To post / reprint the list and/or use GSEDA logo, purchase the RV for $500. View the List for Free.
Details about Sunday night annual update at Omni (Salon AB) at 7 pm, Monday morning DAC pavilion panel & Monday afternoon panel
A ppt description of Gordon Bell’s Law and some Semiconductor Design best practices. Feel free to add your own Methodology Laws, Tips and Tricks to this Presentation and send them back. We will add them to the presentation on the EDP and GSEDA website for future Methodologists.
An annotated pdf version of my evening keynote: Looking at the realities of today’s design flows and a brief look at EDA vendors’ responsibilities as part of the semiconductor design chain.
A Breath of Fresh Air: Review of annual conference. Topics included: Parallel programming breakthroughs, an Honest look at Cloud computing, 3D IC is progressing with links to presentations. Includes my evening keynote: Reality and Responsibility in the EDA Market.
It’s not RISC vs CISC; nor CPU vs GPU; it’s SMP vs AMP and a new heterogeneous microprocessor Cluster architecture I’m calling Domain (or Dwarf) Optimized Processors (DOPs) is emerging. Includes A four part New Vision for Intel and a Suggestion for their next acquisition (NVIDIA).
Review of Jim Hogan keynote Navigating the SoC Era where he discussed the reality of the IP Market. Review of Wally Rhines keynote From Volume to Velocity where he discussed the next challenge of verification is to lower the cost of verification in order to increase the number of SoC design starts, particularly from new start-ups.
Review of Steve Furber Future of Computing keynote where he reviewed the biologically-inspired, massively-parallel architectures of the human brain (with a link to his slides); Review of Philippe Magarshack’s keynote on how Technology R&D brings competitive advantage where he addresses the challenges of being an IDM in a Fab-Lite world; 2 common myths dispelled and growth of conference.
Max, Now you know I believe that most SoC designs will be done in FPGAs and nothing I say here is meant to deny that fact; however your promotion of the myth that FPGAs are driving the ASIC vendors from the battle field is ridiculous…
Product review of Cadence’s enhanced Virtuoso-based product (v6.1). Analysis of custom/ analog flows at lower geometries. Includes table of Top IDMs and Top Fabless companies and their design use at different nodes.
ASP DAC continues the trend, started at IC CAD, of being a growing, technically superior and exciting conference. Review of Dr. Takayuki Kawahara’s Non Volatile Memory and Dr. Ajoy Bose’s Managing Increasing Complexity at Higher Level of Abstraction (ESL) Design keynote
Intel has made their first decision by heavily funding their Fab program. Intel’s new process development and Fab division is the heart of the company. They made their CEO decision. Now, they have to feed the Fab. You probably need to break it up Intel into three parts: Manufacturing, Microprocessor, SoC Platform.
New vendors at DAC often ask, “How do you get on the What to See @ DAC list? “How much does it cost to get on the What to See @ DAC list?” We believe “Thou shalt not be a Coin-operated Analyst!” Here is how the annual list is created.
The key to our strong research is getting to know the right people. The difficulty is getting a hold of them; they are very busy engineers. The easiest way is to know what shows they attend. The DATE technical program seemed like it was custom made for my interest and theirs.
EDA, GPU, Linux, Parallel Computing & EE Times November 8th, 9th & 10th featured three conferences; IC CAD , ARM Techcon and ParCAD, which made for a busy but very interesting week. Just to touch the highlights; IC CAD ran out of printed programs, ARM Techcon featured a new GPU and an open source embedded software effort that should cut the ESL TAM in half (Linaro), and ParCAD proclaimed Parallel computing as just plain hard work.
The year 2009 was a tough one. The only thing keeping EDA from exceeding the negative 11.3% of 2008 was that Cadence had taken its worst financial cuts in 2008 and was in the second year of its negative bubble.
Jem Davies and I have been having a running conversation on Domain Specific, or Application Specific microprocessors. There probably is a set definition for both terms but as they seem to be merging I’ll continue to call then Application Specific for now
A general purpose processor (CPU) is by definition sub-optimal for any specific application. Its strength is in the ability to do multiple applications. That worked fine until we began to run into the power wall a few years ago. We now can no longer afford the luxury of a sub-optimal solution.
This year’s DAC had the right mix of Exhibits, Panels, Technical Sessions and attendees for emerging Electronic System Design (and ESL) Market. Attendance was high quality. Other topics: 3DICs, Peggy, Gadi Singer, Wallcharts and the electric cart experiment.
Ok, so maybe I’m exaggerating, but Moshe’s (Xilinx) keynote at SNUG was certainly the first one I’ve seen. In the 1980s, the FPGA marketing establishment started exaggerating their capabilities. Moshe put an end to the exaggerated marketing claims because at 45nm an FPGA had enough gates to do true SoC designs.
This is a Methodologist’s Conference where presenters come in and present their ideas, not necessarily their conclusions, and then let the audience critique their approach. This makes for a rambunctious program. This year’s topics included: What Comes After CMOS and 3D-ICs.
DATE 2010 was a pleasant surprise and success. The venue was good; the technical conference was excellent; attendance was high quality with the continued shift to Systems and Embedded engineers and the show floor was busy. ‘Why was the show floor so poorly attended by ESL vendors?’ Poor EDA marketing
This was a bad idea to begin with. The only one that had anything to gain was TSMC. By trying to mimic the ARM model, Intel would have only cannibalized their own revenue stream. Intel cannot have it both ways (IDM and Fabless.) This is not a fight to the death.
Intel has made their first decision by heavily funding their Fab program. Intel’s new process development and Fab division is the heart of the company. They made their CEO decision. Now, they have to feed the Fab. You probably need to break it up Intel into three parts: Manufacturing, Microprocessor, SoC Platform.
New vendors at DAC often ask, “How do you get on the What to See @ DAC list? “How much does it cost to get on the What to See @ DAC list?” We believe “Thou shalt not be a Coin-operated Analyst!” Here is how the annual list is created.
The key to our strong research is getting to know the right people. The difficulty is getting a hold of them; they are very busy engineers. The easiest way is to know what shows they attend. The DATE technical program seemed like it was custom made for my interest and theirs.
Mentor’s acquisition of Valor reflects an increasing verticalization of the PCB design to manufacturing market. PCB is one of the most mature segments of the EDA industry. Where it once accounted for the largest segment of EDA revenue, it now represents less than 10% of total EDA revenue.
Tom Starnes had an interesting panel at ARM Techcon this year. The topic of the panel was Cloud Computing but at the end the conversation turned into a look at the competitive battle between Intel and ARM.
Something was different at Hot Chips this year, significantly different: Parallel Computing. The IC industry’s shift from single processor computing to multi-core has moved us away from the Von Neumann compute model to a undefined model… endangering Moore’s Law.
DAC is back. What was most evident was that the sense of community has returned…Social media, Sunday night, my favorite panel, Conference review.
Two acquisitions (Synfora- Esterel; Apache– Sequence) have been taken by some people as a continuation of the asset acquisitions we’ve been seeing recently. This is a continuation of the Gloom and Doom school of thought. Looks like some people are missing the point.
The 14th annual ‘must see’ list of products includes ESL synthesis, ESL power, DRC/ Extraction, ASIC layout and Design Team E&A tools. This year we are going back to the basics. In order to receive permission to post the list on your website, you must purchase the Research Viewpoint
The planned investment in Smart Grids brings opportunities to EDA and Embedded Software companies. Discussion includes definition of smart grid, opportunities analysis, IT spending, and recent Standards activity.
EDP again had an excellent technical program. 4 main themes: Network on Chip (NoC), RTL ASIC Hand-off, Automation of Analog Design and Parallel Computing. Gary takes an Honest Look at Parallelism with discussion of tech sessions and nVidia, Magma keynotes. EDP Presentations
The 5% layoff says that Cadence is recovering faster than expected. On the surface shutting down DFM looks like a good decision…Look a little closer however and it brings up a problem with their long term strategy
Surviving another industry downturn through exploration of IC package and PC Board interfaces. Details opportunities to mitigate effects of downturn and specifically examines opportunity to optimize the Chip-Package-System co-design for competitive advantages.
continuing the re-aggregation of the Semiconductor software stack. Discussion includes motivations and trends with embedded software companies, Intel’s interest in the Embedded Market, where Wind River fits in and Impact on Embedded SW & EDA markets.
Dire predictions for DATE were wrong. The technical show was excellent and my favorite part of DATE, the hallway conversations, was as active as always. Reviews Keynotes and Panels. Discusses the relationship between Marketing, Sales and Trade Shows.
From Von Newmann to Moore’s Law to Threads and Pipe-lining to the Power Crisis to SMP & AMP. Presently we are struggling to come up with a new Compute Model of Computation so that we can develop the SW architecture and tools needed to program multi-core ICs.
The Von Neumann compute model is the sequential single processor architecture found in most computers today. As the Power problem increased, the semiconductor vendors moved to a multi-core architecture…solving the performance problem but abandoning the Von Neumann architecture…putting into jeopardy all the companies that have made a living based on the Von Neumann compute model; Microsoft, Intel.
Intel has made their first decision by heavily funding their Fab program. Intel’s new process development and Fab division is the heart of the company. They made their CEO decision. Now, they have to feed the Fab. You probably need to break it up Intel into three parts: Manufacturing, Microprocessor, SoC Platform.
New vendors at DAC often ask, “How do you get on the What to See @ DAC list? “How much does it cost to get on the What to See @ DAC list?” We believe “Thou shalt not be a Coin-operated Analyst!” Here is how the annual list is created.
The key to our strong research is getting to know the right people. The difficulty is getting a hold of them; they are very busy engineers. The easiest way is to know what shows they attend. The DATE technical program seemed like it was custom made for my interest and theirs.
Congratulations DATE, you’ve pulled it off…becoming a major conference for Embedded Software development, especially that pertaining to Multi-Core/Multi-Processor systems… What was even more impressive was…its intention of becoming a true “systems” design automation (SDA) conference, using this year’s automotive emphasis to bring mechanical design to the table
This year’s DAC was a hard one to classify. However in the last year there were several panels that either questioned the meaning or existence of ESL design. Unless I missed something, there was nothing along these lines at DAC 2008. Somehow it had been replaced with an acceptance that like it or not we had entered the ESL area.
This year’s EDP conference in April focused on the continuing evolution of multi-core systems and their associated design problems. Semiconductor vendors reflected upon the difficulty of programming multicore platforms, the lack of software that could exploit the concurrency of the multicore design and the limiting nature of memory latency that holds down system speed…
GS EDA has been interviewing companies to uncover whether “Is 2008 going to be the year where analog design automation moves forward and catches up with digital design automation?” While there has been a shift away from in-house proprietary solutions to design tool integration, will DAC be the turning point?…
Trip report includes discussion of Jan Rabaey (UC Berkeley) keynote address, System-Level Design versus ESL versus System Design Automation, Network on Chips, model-based ESL versus language-based ESL, F.C. Tseng (TSMC) keynote address, Semiconductor Research Consortia, and Restrictive Design Rules…
While there have been some complaints on the quality of education for the new EE graduates, our experience has been positive…Recently some professors have been talking about a new engineering curriculum for embedded designers… We are seeing the need for an engineering curriculum for an entirely new breed of engineer…
Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.
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