Archives for Industry Notes

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  IC CAD, ARM Techcon & ParCad Review

  EDA, GPU, Linux, Parallel Computing & EE Times November 8th, 9th & 10th featured three conferences; IC CAD , ARM Techcon and ParCAD, which made for a busy but very interesting week. Just to touch the highlights; IC CAD ran out of printed programs, ARM Techcon featured a new GPU and an open source embedded software effort that should cut the ESL TAM in half (Linaro), and ParCAD proclaimed Parallel computing as just plain hard work.
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  Cost: FREE

  
  

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  2010 Market Trends: Executive Summary

  The year 2009 was a tough one. The only thing keeping EDA from exceeding the negative 11.3% of 2008 was that Cadence had taken its worst financial cuts in 2008 and was in the second year of its negative bubble.
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  Cost: FREE

  
  

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  Optimize despite Amdahl’s Law

  Jem Davies and I have been having a running conversation on Domain Specific, or Application Specific microprocessors. There probably is a set definition for both terms but as they seem to be merging I’ll continue to call then Application Specific for now
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  Cost: FREE

  
  

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  Sub-Optimal Processing

  A general purpose processor (CPU) is by definition sub-optimal for any specific application. Its strength is in the ability to do multiple applications. That worked fine until we began to run into the power wall a few years ago. We now can no longer afford the luxury of a sub-optimal solution.
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  Cost: FREE

  
  

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  DAC 2010 – The Turn-a-Round DAC

  This year’s DAC had the right mix of Exhibits, Panels, Technical Sessions and attendees for emerging Electronic System Design (and ESL) Market. Attendance was high quality. Other topics: 3DICs, Peggy, Gadi Singer, Wallcharts and the electric cart experiment.
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  Cost: FREE

  
  

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  The First Honest FPGA Pitch

  Ok, so maybe I’m exaggerating, but Moshe’s (Xilinx) keynote at SNUG was certainly the first one I’ve seen. In the 1980s, the FPGA marketing establishment started exaggerating their capabilities. Moshe put an end to the exaggerated marketing claims because at 45nm an FPGA had enough gates to do true SoC designs.
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  Cost: FREE

  
  

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  EDP 2010 – A Look at the Future of IC Design

  This is a Methodologist’s Conference where presenters come in and present their ideas, not necessarily their conclusions, and then let the audience critique their approach. This makes for a rambunctious program. This year’s topics included: What Comes After CMOS and 3D-ICs.
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  Cost: FREE

  
  

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  DATE 2010: a Missed Opportunity for ESL Vendors

  DATE 2010 was a pleasant surprise and success. The venue was good; the technical conference was excellent; attendance was high quality with the continued shift to Systems and Embedded engineers and the show floor was busy. ‘Why was the show floor so poorly attended by ESL vendors?’ Poor EDA marketing
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  Cost: FREE

  
  

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  Intel & TSMC: A Bad Deal

  This was a bad idea to begin with. The only one that had anything to gain was TSMC. By trying to mimic the ARM model, Intel would have only cannibalized their own revenue stream. Intel cannot have it both ways (IDM and Fabless.) This is not a fight to the death.
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  Cost: FREE