Gary Smith EDA Consulting in Electronic Design

Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.

  • Archives for Industry Notes

    • Synopsys/ Magma - Great Acquisition, Difficult Merger

      Analysis of the Synopsys/ Magma tool sets: why Synopsys bought Magma, what tool markets will be affected and how it will affect the design engineer. Complications with merging the R&D teams. Will Synopsys be able to do a better job than they did with Avanti?
    • Cost: FREE


    • IBM's Transactional Memory

      Why IBM uses Transactional Memory (reliability and parallel computing) and the importance of memory architectures.
    • Cost: FREE


    • IC CAD and Transactional Memory

      The Virtual World is decreasing the sharing of peripheral information. At IC CAD, I learned that IBM is using Transactional Memory in its Super Computer.
    • Cost: FREE


    • The Gigahertz Joke

      Dynamic Power in an SoC is controlled by two major variables; Gate Count and Frequency. Once the Power Budget is set, as in the case of mobile designs, designers must trade off these two variables. As the demand for more gates is growing designers are looking at lowering the average frequency of their designs. Microprocessor vendors that are still bragging about their Gigahertz processors are missing the point.
    • Cost: FREE


    • Atoptech Shows Explosive Growth

      After we published IC CAD 2011 Market Trends report, we were informed that we had significantly underreported Atoptech. They had actually grown an amazing 187% in 2010. Includes ASIC Market Trends pie chart of vendors
    • Cost: FREE


    • ARM TECHCON 2011 – The Week The World Changed

      Ok, I’m exaggerating; this change has been going on for weeks. It’s just that going to ARM TechCon made the change obvious. By the time you left TechCon your view, one way or another, of mainstream computing had changed significantly. Either that or you weren’t paying attention.
    • Cost: FREE


    • 2011 Complete Market Trends: Executive Summary: EDA Grows Again

      It’s good to grow. Growth doesn’t solve all problems but it helps. The Market Trends Executive Summary includes analysis and figures of EDA market share of major players and 5 year market forecast growth per major application.
    • Cost: FREE


    • Responsibility of the Semiconductor Design Infrastructure

      How R&D can solve the HW cost problem through review of reuse, number and size of design blocks, engineers per block and EDA tools. EDA is Responsible for developing design tools that enable the IC design process, at a design cost that allows the ecosystem to operate at a profit?
    • Cost: FREE


    • TOP Four Semiconductor Companies in Design

      My analysis of why NVIDIA, Samsung, STMicro and Broadcom are the top four semiconductor companies for designing chips and why.
    • Cost: FREE


    • Apache Acquisition

      Review of Apache aquisition by ANSYS: terms, product analyses and how the joint solutions will affect customers (EMI, thermal analysis, signal & power integrity).
    • Cost: FREE


    • Variation Analysis And Design For Custom ICs Across SOC

      Once we reach 65nm silicon, variation became a major factor in SOC design.
    • Cost: FREE


    • The History of the ITRS Cost Chart

      A description of the origins, methodology, elements and working group practices for the ITRS cost chart.
    • Cost: FREE


    • DAC 2011: The Feel Good DAC

      Review of my Sunday night talk, keynotes, Word on the Street from engineers about Mentor, Magma, Apache, Cadence and Synopsys. Who’s up and who’s not? Includes ITRS Cost Chart from Sunday Night talk.
    • Cost: FREE


    • IP Reuse & Design Manageme nt in the SoC & IC Design Process

      The increase use of IP has driven the need for sophisticated Design Management tools. This Industry Note looks at an user survey and need for Design Management tools in the SoC and IC Design process.
    • Cost: FREE


    • What To See at DAC List

      16th annual list of 'must see' products at the 48th DAC 2011. To post / reprint the list and/or use GSEDA logo, purchase the RV for $500. View the List for Free.
    • Cost: FREE


    • Gary Smith EDA DAC 2011 Activities

      Details about Sunday night annual update at Omni (Salon AB) at 7 pm, Monday morning DAC pavilion panel & Monday afternoon panel
    • Cost: FREE


    • Bell's Law and Tips, Tricks + Best Practices in Semiconductor Design Methodology

      A ppt description of Gordon Bell's Law and some Semiconductor Design best practices. Feel free to add your own Methodology Laws, Tips and Tricks to this Presentation and send them back. We will add them to the presentation on the EDP and GSEDA website for future Methodologists.
    • Cost: FREE


    • Reality and Responsibility in the EDA Market (EDP 2011)

      An annotated pdf version of my evening keynote: Looking at the realities of today's design flows and a brief look at EDA vendors' responsibilities as part of the semiconductor design chain.
    • Cost: FREE


    • EDP 2011

      A Breath of Fresh Air: Review of annual conference. Topics included: Parallel programming breakthroughs, an Honest look at Cloud computing, 3D IC is progressing with links to presentations. Includes my evening keynote: Reality and Responsibility in the EDA Market.
    • Cost: FREE


    • The New Microprocessor Architecture: There isn’t one!

      It's not RISC vs CISC; nor CPU vs GPU; it's SMP vs AMP and a new heterogeneous microprocessor Cluster architecture I’m calling Domain (or Dwarf) Optimized Processors (DOPs) is emerging. Includes A four part New Vision for Intel and a Suggestion for their next acquisition (NVIDIA).
    • Cost: FREE


    • DATE 2011 - DATE Continues to Grow

      Review of Steve Furber Future of Computing keynote where he reviewed the biologically-inspired, massively-parallel architectures of the human brain (with a link to his slides); Review of Philippe Magarshack's keynote on how Technology R&D brings competitive advantage where he addresses the challenges of being an IDM in a Fab-Lite world; 2 common myths dispelled and growth of conference.
    • Cost: FREE


    • FPGAs Taking Over the ASIC Market is a Myth

      Max, Now you know I believe that most SoC designs will be done in FPGAs and nothing I say here is meant to deny that fact; however your promotion of the myth that FPGAs are driving the ASIC vendors from the battle field is ridiculous...
    • Cost: FREE


    • Custom/Analog Design Developments Meeting 65nm And Below Challenges

      Product review of Cadence's enhanced Virtuoso-based product (v6.1). Analysis of custom/ analog flows at lower geometries. Includes table of Top IDMs and Top Fabless companies and their design use at different nodes.
    • Cost: FREE


    • ASP DAC is Doing Well

      ASP DAC continues the trend, started at IC CAD, of being a growing, technically superior and exciting conference. Review of Dr. Takayuki Kawahara's Non Volatile Memory and Dr. Ajoy Bose's Managing Increasing Complexity at Higher Level of Abstraction (ESL) Design keynote
    • Cost: FREE


    • ESL Behavioral Design

      Which engineers use it and the 3 virtual prototypes
    • Cost: FREE


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