IS 2008 THE YEAR FOR ANALOG/MIXED-SIGNAL?

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  The Analog Survey
  
  Since the first of this year, Gary Smith EDA has been interviewing and surveying companies in the Analog/Mixed-Signal EDA landscape to uncover answers to the question “Is 2008 going to be the year where analog design automation moves forward and catches up with digital design automation?”
  
  According to the majority of Analog/Mixed-Signal Design Tool start-ups, the market for custom IC design solutions, which includes analog/mixed-signal designs, could reach $700 million in 2008. The Gary Smith EDA forecast for Custom Analog/Mixed-Signal ICs is $427 million in 2008. The majority of this growth is being driven by the wireless and consumer market applications. Thus a huge opportunity exists for 100 percent automation in analog/mixed-signal, if the layout tools existed. According to the majority of all interviewed and surveyed, the process is still predominately manual, and most of the older tools are insufficient for designs below 90nm. No one has yet to make an automated custom layout tool acceptable to analog/mixed-signal device designers. The industry is lagging as it deals with “your grandfather’s analog design process”.
  
  Analog EDA
  
  Except for the majority of EDA start-ups, many listed in Figure 1; most of the tools being used in the analog/mixed-signal design flow today are pre-1998 generation. Analog/Mixed-Signal design flows now range from 9 months to as long as 18 months, especially for high-end design applications. Users like Texas Instruments, STMicroelectronics, Qualcomm and Broadcom are shifting mixed-signal designs (also called ASPs and ASSPs) to 65nm and 45nm processes in 2008 and 2009. If they could automate layout. physical design would be measured in days and
• not weeks or months.
  
  The value to these companies and their designers would include:
  
  • Faster delivery time to market
  • Better opportunity for increased revenue from IP re-use and process node migration
  • Better quality of result (QoR) at process technology below 65nm
  
  
  FIGURE 1
  Analog/Mixed-Signal EDA Landscape
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  Mary A. Olsson
  
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