Surviving Another Industry Downturn: A Time for Opportunities

• Industry Cycles
  
  For some companies involved in the volatile electronics industry, upturns and downturns are cyclical, challenging and full of opportunities. Some companies take the challenges and turn them into opportunities by:
  
• • Employing inventory management programs to reduce product manufacturing
  costs and prices
  • Developing new contracts to maintain customer loyalty and out-survive competitors
  • Changing pricing strategies and contracts with foundry partners
  • Expanding IP partnerships
  • Selling off or closing old fabs rather than invest in upgrades
  • Upgrade fabs for new products or technology: solar, MEMs, etc.
  • Developing multi-tiered prices and product lines
  • Refocusing market strategies on new applications and new users
  • Acquiring companies to gain technology or engineering expertise
  • Qualifying tools and solutions for foundry manufacturing processes
  
  
• In 2006 GSEDA made several recommendations on future growth opportunities for EDA and chip designers:
• 
  • Increased production of 65nm and 45nm designs
  • RF circuitry needs and competing strategies driving “exponential growth in functionalities that must be integrated into the same sized and same priced” SIP versus SOC
  • Package-on-package (PoP) and die-to-die package solutions
  • PCB and package design challenges would be new 4G wireless applications that must remain “backward compatible with 3G/2G modes
  • Concurrent team design infrastructures or models, between “IC layout and manufacturing (foundries at front-end and back-end) were needed to meet process effects, photolithography, data volumes, and cost effective chip yield”. Applications like those illustrated in Figure 1 were pushing the limits of existing package, board and system design engineering capabilities and EDA software tools.



Source: Cadence & GSEDA April 2009

Today multiple EDA companies now offer a variety of co-design platforms or concurrent software sections to bridge the design gaps from silicon to package and board to system. Their platforms required more partnering with silicon and package foundries and board to system level manufacturers. This perspective will cover a selected number of companies that recently introduced and compete in co-design platforms for both the front-end and back-end of design.

EDA Vendors: Chip-Package-System Co-Design

There is a growing list of EDA vendors paying homage to the chip foundry and SATS vendors to optimize interconnect across the entire chip-package-board domain via co-design solutions. By taking an aggressive position in co-design they build customer relationships and see it as an opportunity to get ahead of competitors. Two specific EDA companies significantly involved in the introduction of advanced co-design platforms are Apache Design Solutions and Agilent EEsof EDA Division. Both companies partner or work with the two largest suppliers of concurrent Package-Board-System co-design solutions: Cadence and Mentor Graphics.

Apache Design Solutions, a start-up founded in the 2001 downturn, acquired Optimal in 2007. Optimal’s technology base included 3D power, signal, and thermal analysis solutions for packages, System-in-package (SIP) and board designs. Today Apache claims to lead the EDA industry with 100% focus on power and noise analysis co-design solutions from IC to the package domain via their Sentinel product. The Sentinel product line is targeted at 45nm and below designs with special emphasis on 3D and TSVs (through silicon vias).

Agilent EEsof introduced its ADS 2009 HF/High speed front end (simulation and verification) co-design platform in 2009. Their front-end solution is in contrast to the Cadence and Mentor back-end co-design platforms. The ADS 2009 co-design “sweet-spot” is their strength in the RF domain. As stated by Agilent “the RF physical layer of any wireless system requires the successful integration of mutli-technology components to meet wireless system specs such as LTE, WiMax, WiMedia, Wireless HD, etc.

Concurrent Infrastructures

The EDA industry currently does not have a concurrent software development infrastructure in place. However, companies like Agilent EEsof, Apache, Cadence and Mentor; are pushing the limits of software technology to achieve interoperability. No one company has yet to achieve a complete software model from concept to complete system. As noted by GSEDA in November 2008, the cost of developing embedded software across the entire food chain is excessive. In 2007 the cost of developing the embedded software for an SOC (System On Chip) or an NOC (Network On Chip) passed the cost of designing the SOC/NOC.

Advancements in Co-Design

As noted by all four companies co-design of an IC, package/module and board before fabrication, or as soon as they become available either in the form of simulated designs or off-the-shelf parts reduces the risk of failure and delay. “If one extrapolates this risk reduction to a complex wireless or hi-speed communication system, the ROI is significant in the reduction of time, as it shortens the design cycles, and cost of work”.

Mary Ann Olsson