Gary Smith EDA Consulting in Electronic Design

Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.

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    The History of the ITRS Cost Chart

    The History of the ITRS Cost Chart

    The History
    At the end of last century a chart started appearing in presentations that tracked the growth in semiconductor design productivity compared to the growth in the number of gates available to the design engineer. That chart was presented in the Semiconductor Industry Association International Technology Roadmap for Semiconductors: 1999 edition (ITRS). Its point was that the number of gates available to be designed by a design team was outgrowing the increase in design productivity. This became known as the Design Gap Chart (See Figure 1).

    Figure 1 – The Design Gap Chart
    Source: SEMATECH

    I pointed out to a member of the Design TWG (Technical Working Group) that, although the point was interesting, the actual numbers were incorrect. I had clients that had no problem using all available gates, and would continue to do so in the near future.

    I had been using a design pyramid to describe the different levels of design; Power Users, Upper Mainstream Users, Lower Mainstream Users and Late Adopters. As far as I could tell the chart tracked the productivity of Upper Mainstream Users who had small CAD groups and relied entirely on commercially available design tools. The Power Users had strong CAD groups and developed leading edge design tools in-house and had been keeping up with the gate count growth (See Figure 2).
    Figure 2 – The Semiconductor Design Pyramid
    Source: Gary Smith EDA

    This had come about based on a widely held view that, with the maturing of the EDA industry, users no longer needed to invest in expensive CAD teams and internal tool development. Of course many companies didn’t need to stay on the leading edge of design, but for those that did the investment in CAD and In-House tools was vital. I was invited to be on the ITRS Design TWG and asked to take over the Cost Chart project. I accepted and the first of present version of the cost chart was published in 2001 (See Figure 3).

    Figure 3 – ITRS Cost Chart 2001
    Source: ITRS 2001
    The ITRS is managed by SIA and has become the International Technology Roadmap for Semiconductors. It is an all-volunteer organization of engineers and academics that wish to further the growth of the semiconductor industry. The model worked so well for the semiconductor equipment manufacturing industry that it has spread to all factors of semiconductor design and manufacturing. Let’s face it; if you don’t have a roadmap, it’s hard to plan your R&D efforts.

    The ITRS Cost Chart Methodology

    The International Technology Roadmap for Semiconductors is sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. The sponsoring organizations are the European Semiconductor Industry Association (ESIA), the Japan Electronics and Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), the Taiwan Semiconductor Industry Association (TSIA), and the United States Semiconductor Industry Association (SIA). It includes most of the major semiconductor companies in the world, all of which have the opportunity to participate in and review all outputs of the Working Groups, or TWGs. The working groups go beyond that by accepting any qualified engineer, academic or research scientist that is willing to put in the time and effort to help put together the yearly report.

    Many of the parameters are set at group level and handed down to the TWGs, such as the official nodes. This way multiple TWGs will be working with the same top level inputs. We then survey a set of the member companies for our inputs. Most TWGs are international, greatly helping the survey process. The Design TWG has members from Europe, the US and Japan. We have consistently been able to get input from the other non-represented areas. It was especially true when I added software to the Cost Chart. Asia played a big part in supporting my data-gathering. The final report is an average of the parameter being measured, however it is important to know just what is being measured.

    The following parameters are handed down:
    • Node
    • Max Gates in Millions

    The following parameters are surveyed:
    • Cost of one seat of design tools for one year
    • Size of an average High End Design in millions of gates
    • % memory Utilization
    • Reason for Productivity Improvement

    The one area we do not use averages is in the cost of an engineer. As design teams are spread around the world we have chosen to use the worst case scenario; that is the salary and overhead of a Silicon Valley design engineer. Some of the companies have chosen to plug in their own engineering cost and it’s easy to do.

    The difference in this Cost Chart is that we don’t try to just plot data points but we do our best to find out what happened to increase productivity. In fact, being a roadmap we attempt to predict what methodology or tool change will be required to cause the productivity improvement. We aren’t always right but my experience has been that the technology community is pretty accurate within a five year window. Further out they have a good idea what needs to happen; it’s just harder to get the timing down.

    In Conclusion

    So there it is, no magic, no secret formulas, all pretty much out in the open and, best of all, free. We are just a bunch of engineers doing their best to further the health of the semiconductor world. And all you have to do is ask.

    To view entire paper, download the PDF here

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