Gary Smith EDA Consulting in Electronic Design

Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.

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    FPGAs Taking Over the ASIC Market is a Myth
    FPGAs Taking Over the ASIC Market is a Myth Max, Max, Max – Now you know I believe that most SoC designs will be done in FPGAs and nothing I say here is meant to deny that fact; however your promotion of the myth that FPGAs are driving the ASIC vendors from the battle field is ridiculous. First of all I recommend you contact Bryan Lewis at Gartner-Dataquest. He’s been producing his Design Start report for well over 15 years now and it is considered the bible in this area.

    Let’s look your statement that “FPGAs can now play in applications and markets that were previously owned by ASICs”. Your assumption seems to be that technically these designs are stagnant. Now I’m sure that an FPGA can be used in the design of a cell phone, circa 1998, but things have changed a bit. As FPGAs are reaching tens of millions of gates, ASICs are now shooting for a billion gates. As the functionality increases so does the ASIC gate counts.

    The biggest surprise in my recent Design Seat Count report was the 10% decline in FPGA seats during the Great Recession. It turned out that the recession wasn’t the main cause of the decline. I remember being on a panel with Wes Paterson, when he was VP of Marketing for Xilinx. We were discussing the difference between FPGA gates (or Paterson Gates as we fondly called them) and ASIC gates. Wes made the statement that the main difference was that you didn’t need to simulate an FPGA gate. Well the days of Blow and Go designing are Blown and Gone. Now designing an FPGA SoC is just as challenging as designing an ASIC SoC. The skills of today’s FPGA designer have been ratcheted up quite a few notches and this has caused us to lose design seats over the past few years. The only difference between the two designers today is the quality of their design tools and once FPGA designs start exceeding forty million gates that will have to change too.

    Your good friend,
    Gary

    To view entire paper, download the PDF here

    Comments

    • Max Maxfield of Maxfield High-Tech Consulting said on Mar 24th, 2011 11:41:39 AM
      Gary old bean, where in the above article did I say that "FPGAs are driving the ASIC vendors from the battle field"?

      All I said was that there are fewer ASIC design starts than there used to be and more FPGA design starts than there used to be. Also that the capacity and performance of today's state-of-the-art FPGAs means that they can now play in applications and markets that were previously “owned” by ASICs and other devices.

      But I by no means believe that ASICs are headed to a long retirement in Florida -- ASICs / ASSPs / SoCs will be with us in one form or another for ever (well, at least as long as you or I are around to waffle on about them :-)
    • Alec Stanculescu of Fintronic USA, Inc. said on Mar 24th, 2011 12:45:22 PM
      Gary,

      Your dicussion with Wes Peterson is very telling of the situation. The key is EDA tools that can support ASIC and FPGA design. With the complexity growing, even FPGA design, where the turnaround is much cheaper than that of ASIC design, is hard without the most efficient EDA tools. For a tool to be efficient, both the level of abstraction of the specification (e.g. math level) and the lower level, from where synthesis tools can automaically make the FPGA or ASIC(e.g. RTL) must be part of the same language in order to have the most efficient design environment.

      This is what FinSim's support for Verilog and FinSimMath brings: Verilog and Math level in the same language. For a comparison between FinSimMath and MatLab please look at https://www.fintronic.com/lsim1.html.
      For more info on FinSimMath please look at https://www.fintronic.com/finmath.html.

      Thee design productivity increase brought by merging in the same language the source and the target levels of abstraction is similar to what Verilog and VHDL did by merging RTL and Gate levels. We all know what productivity increase that merging brought.

      Best regards,

      Alec
    • Lou Covey of Footwasher Media said on Mar 24th, 2011 06:18:27 PM
      ASICS not going the way of the dinosaur, but the edge in design innovation goes to FPGAs. Very few people can survive in the SoC world financially unless they are doing an ARM core or an FPGA. That's also becoming true in the systems world as more and more systems manufacturers are looking at FPGAs.
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