Gary Smith EDA Consulting in Electronic Design
Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.
2007 Archives
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Jan
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Chip Design Magazine
Future Verification Appears Uncertain -
SCD Source
Sequential equivalence checker supports C synthesis tools -
SIGDA
"Can We Still Keep The Faith?" -
SCD Source
EDA applications move to parallel computing -
Semiconductor International
Semiconductor Experts Cautious in 2008 -
DACeZine
vol.3/ issue 5 -
SCD Source
Imperas preps multicore virtual platform tools -
SCD Source
Ten 2008 trends in system and chip design -
SCD Source
Virtual platforms - a reality check, part 2 -
ACM/SIGDA
event coverage
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Feb
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EE Times India
Revisiting the discussion on fabs in India -
DVCon:
Cooley’s Panel to Focus on Troubles in EDA -
EE Times:
Statistical timing analysis moving to transistors -
EE Times:
Sparks fly at EDA 'troublemakers' panel -
EDN:
EDA Troublemaker panelists sing “Kumbaya?” -
EE Times
SysVerilog support falls short for design -
EE Times
Blaze lights DFM fire in merger with Aprio
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Mar
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EE Times
EDA startup looks to verify verification -
EE Times India
India's semiconductor policy: The ongoing debate -
EE Times
Commentary: EDA is dead, software lives -
Electronicstalk
Variability analysis software on award shortlist -
EE Times
Report: 11 percent EDA growth in 2006 -
EE Times Asia
EDA industry grew 11% in 2006, says report -
EE Times
Patent resolution removes cloud over Magma -
EE Times Europe
What is Imperas thinking? -
EDA Tech Forum
Start Here
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Apr
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EE Times India
Are you laying bricks or building a palace? -
EE Times
Ada 2005 speaks to real-time embedded applications -
EE Times
EE Times EDAC: EDA up 15 percent in 2006 -
DAC
12th Annual Workshop for Women in Design Automation (WWINDA) to Focus on “Managing Your Career” -
Programmable Logic Design Line
Free cell-phone locator website -
EDN
Lessons learned from four failed electronics mergers -
EDN
Voices: Analyst Gary Smith: Semiconductors need a parallel-processing language -
EE Times Asia
EDA industry saw 15% growth in 2006, reports EDAC -
Business Wire
Mentor Graphics Launches Veloce -
EE Times
Mentor, EVE take fresh look at hardware-assisted verification -
EE Times Europe
A new 'DATE' for hardware-assisted verification -
EE Times
Esterel design language seeks IEEE nod -
EE Times
Panel wrestles with field programmable, SOC dilemma -
EE Times
Design-for-manufacturing mantra: Simplify, simplify -
EDA Tools Café: DATE 2007:
Secrets et Surprises à la Côte d'Azur -
MEPTEC Report
"Design and Pray-The Industry Disconnect" -
edacentrum: edaTrendDATE07
Wanted: Compilers for Utilizing MPSoCs
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May
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IEEE VLSI Test Symposium
Test Industry’s Leading Technical Forum Celebrates 25th Anniversary -
EE Times
Constraints open new EDA standards battleground -
EE Times India
The Challenge of Multi-core -
EE Times
IC verification startup takes graphical approach to test generation -
EE Times
System-level synthesis scheme homes in on low-power IC design -
Innovate Forum
Oracle Adds to PLM's Strategic Weight As Enterprise Tool With Agile Acquisition -
Yahoo! Finance
Gary Smith EDA Continues the Annual Tradition of Providing the Latest Design Flow Information at GSEDA @ DAC -
EE Times
Multiprocessing used to break EDA timing bottleneck -
EDA Tech Forum
DAC past, present and future -
EDA Geek
Gary Smith EDA to Present at DAC -
EE Times
Multiprocessing used to break EDA timing bottleneck -
EDN.com
Must see at DAC 2007 lists -
Synplicity.com
Synplicity to highlight vision for high-productivity ASIC & ASSP verification at DAC 2007
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June
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EDN:
EDA Analyst Gary Smith posts "what to see at DAC" list -
EE Times
Design gears up for future -
EE Times
EDA 'software challenged,' Gary Smith says -
YouTube
Gary Smith - Pre DAC Analysis -
EE Times
Analysis: Synplicity's 'Hardi' ASIC prototyping play -
Business Wire
44th Design Automation Conference (DAC) a Success with Attendees and Exhibitors -
EE Times
Bidding for top spot in IC design, Mentor buys Sierra -
EE Times
Competitors disdain Mentor's Sierra acquisition -
TheStreet.com
Mentor Graphics Grabs Chip Tools Maker -
EE Times
Oasis moves slowly as GDSII replacement -
EDN
Another Grim Day for EDA: Richard Goering laid off from EE Times--CMP layoffs -
EDACafe
DAC 2007 – Perceptions of Primacy in Pleasantville -
EE Times India
Design automation: Moving up from the plateau -
EDA DesignLine
The Week after DAC: some lingering thoughts -
DeepChip
The Wiretap -
EDA DesignLine
EDA Shocked Into Action -
DeepChip
The Wiretap -
EDN
Refining multicore concepts, part one -
DeepChip
The Wiretap -
EDN
EDA’s ESL vendors--Unite and take over!...or at least get organized -
EDACafe
EDA Careers Corner post DAC report - from a recruiter’s perspective -
Programmable Logic DesignLine
Programmable Logic DesignLine Engineering Blog
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July
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EE Times
Semicon panel: Design-for-manufacturability no longer a luxury -
New Electronics
Reading the runes -
DeepChip
ESUNG Post 467 -
edacentrum: edaTrendDAC07
“To Bring Designers Over to the Sunny Side” -
edacentrum: edaTrendDAC07
“EDA is Multi-Core, EDA is Parallelism, EDA is Software” -
edacentrum: edaTrend DAC07
“What’s Hot and What’s Not? -
DeepChip
Cooley Does Gary Smith
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Aug
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Portable Design
ESL Tools Come of Age -
Solid State Technology
Will RDRs lead to a resurgence of in-house design tools? -
Components in Electronics
The INMOS legacy -
Semiconducter International
Cadence Acquires Clear Shape Technologies -
Mentor Graphics'
Q2 Financial Results
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Sept
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EDN
Who is the EDA leader in SystemVerilog simulationPart 1 -
EDN
Who is the EDA leader in SystemVerilog simulation?Part 2 -
EDN
Who is the EDA leader in SystemVerilog simulation?Part 3 -
TheStreet.com
Mentor Could Lead Chip-Design Software -
EDN
I’m no one trick pony! -
Business Wire
DAC Unveils New Web Site, Revamps e-Newsletter -
EE Times
Gary Smith to receive ACM Award -
Press Release
ACM/SIGDA Recognizes Analyst Gary Smith’s Two Decades as Chief EDA Analyst -
EE Times
Viewpoint: Is ESL for everyone? -
CNNMoney.com
Synopsys Announces DesignWare System-Level Library -
IQ Online
ACM/SIGDA Special Service Award To Industry Analyst -
SCDsource
Will Pyxis router 'yield' a DFM breakthrough? -
SCDsource
Mathworks C generation may boost algorithmic design
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Oct
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SCDsource
Will Magma's Rio acquisition boost chip/package co-design? -
SCDsource
Magma offers its first ATPG too -
Solid State Technology
Verdict: Cadence+Invarium deal seems a "win-win" -
EE Times Europe
French startup brings DFT to a higher level -
SCDsource
Startup lifts design for test to register-transfer level -
EE Times
Startup Vayavya unveils automated device driver generator -
EE Times Asia
Software drives prototyping for ASICs, SoCs -
Chip Design Mag
Do Verification Engineers Have the Odds Stacked Against Them?
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Nov
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DATE Press Release
DATE'08 ICM, Munich, Germany 10-14 March 2008 -
SCDsource
ICCAD debate: Multicore disaster or opportunity? -
Businesswire
Synplicity Joins Xilinx ESL Design Ecosystem -
Electronicstalk
Software for Xilinxelectronic system level design
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Dec
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SCDsource
Startup Atoptech challenges IC design leaders -
EDN
EDA ESL startup Imperas close to launch -
Semiconductor International
Webcast: 2008 Semiconductor Industry Forecast -
EDN
EDA ESL startup Imperas close to launch
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DV Con Panel: Where Does
Wed Feb 27, 2013 8:30-10:00
Design End & Vrfcn Begin?
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Chip Design
Industry Rethinks RTL Synthesis -
Science Web Hosting Geeks
Menadžment Dizajna & Studija Ponovne upotrebe IP -
NewTechPress
Gary Smith considers the quest for the $10K chip -
Market Watch
Atrenta Number Two in RTL Power Analysis According to Gary Smith EDA -
ARMdevices.net
Video: Gary Smith EDA’s impressions on ARM Techcon 2012
