Gary Smith EDA Consulting in Electronic Design
Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.
2008 Archives
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Jan
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ACM/SIGDA
event coverage -
SCD Source
Imperas preps multicore virtual platform tools -
SCD Source
Ten 2008 trends in system and chip design -
SCD Source
Virtual platforms - a reality check, part 2 -
SCD Source
EDA applications move to parallel computing -
Semiconductor International
Semiconductor Experts Cautious in 2008 -
DACeZine
vol.3 / issue 5 -
SIGDA
"Can We Still Keep The Faith?" -
SCD Source
Sequential equivalence checker supports C synthesis tools -
Chip Design Magazine
Future Verification Appears Uncertain -
Electronicstalk
IP programme shows initiative for FPGA designers -
SCD Source
Ten 2008 trends in system and chip design -
SCD Source
Infineon's Jürgen Karmann on power and reliability -
EDA Confidential
Sigh, Sigh...Kiss EDAC Goodbye -
EE Times
Is Mentor's Rhines too nice for takeover battle? -
EE Times
Mentor bid: There will be blood -
EE Times India
IPL alliance creates buzz on analogue design -
EE Times India
Cadence's CEO Fister: Driven by ambition -
EE Times India
Will Mentor fight the offer of Cadence -
Dataweek South Africa
Altium tops poll of best PCB layout tools
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Feb
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DesignCon 2008
Breker Verification Systems to Speak Out on Coverage-Driven -
EE Times
Putting the system in electronic system design -
Semiconductor International
2008 Economic Forecast: Fairly Unpredictable -
Market Wire
Is U.S. Chip Industry on Fast Track to Innovation? -
EE Times
Putting the system in electronic system design -
EE Times
EDA startup offers 'elastic clocks' as cure for variability -
EDN
IC verification key: 'Do it step by step, don't cut corners' -
SCD Source
Is DFM a vitamin or a cure? -
EDN
Where's the ROI in DFM? -
EarthTimes.org
Don't Miss Cooley's Troublemakers Panel at DVCon 2008 Next Week -
EE Times
PCB tool vendors reference chart -
Market Wire
Mentor Graphics Delivers Breakthrough in Verification Intelligence -
EE Times
Mentor raises SoC verification intelligence -
EDN
Mentor adds verification intelligence to Questa platform -
Fox Business
Synfora Joins Xilinx ESL Initiative Ecosystem -
Electronicstalk
Acceleration technology uses graphics processors -
SCD Source
Analog experts call for new methodologies
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Mar
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Business Wire
DATE Panel on Concurrency in Multiprocessor World Features Imperas -
portal.acm.org
What's the next EDA driver? -
synopsysoc.org
Analog Insights » Blog Archive » More “black magic” mumbo jumbo ... -
GlobalSpec
Reference chart for Printed Circuit Board (PCB) design tools -
SCDsource
Gary Smith EDA has identified the rewriting of tools for parallel computing as the issue with the "largest ... -
SCDsource
What's interesting about Gauda -
Electronic Design Process 2008 Symposium
Advance Program -
EDA cafe
First 4 weeks of Shock & Awe … then DVCon ... -
DSP DesignLine
DSP Tools, Software, and RTOSs -
Reuters
Synfora Joins Xilinx ESL Initiative Ecosystem -
Silobreaker: Ning
All Our Charts Point Up And To The Right -
Telecom market news
Third Multicore Expo U.S. Set for April 1 - 3 ... -
Electronics Talk
Acceleration technology uses graphics processors: News from Gauda -
Gauda, Inc.
Gauda, Inc. Announces Breakthrough for Accelerating OPC and ... -
EETimes
Gauda accelerates OPC verification -
EETimes
Patent resolution removes cloud over Magma -
SCDsource
Gary Smith EDA said that Titan is "very ambitious, copying the productivity capabilities of the ASIC layout .. -
SCDsource
Gary Smith EDA has identified the rewriting of tools for parallel computing as the issue with the "largest ... -
Semiconductor
Gauda, Inc. Announces Breakthrough for Accelerating OPC and ... -
Audio DesignLine
EDA Reference Chart: PCB design tools | Audio DesignLine -
EDA geek
DATE 2008 Features Panel on Concurrency in a Multiprocessor World -
Embedded Computing
DATE'08-Europe's must-attend event for the semiconductorand ... -
Technorati
Discussion about “Micrologic Releases nanoRV -
DATE 08 Exhibition Prog
Gary Smith EDA, USA 4. Matthias Voigt, General Manager of Electronics Europe Engineering Group, NEC, Germany ... -
DAC Newletter
Gary Smith EDA believes that at least some of the difficulties associated with automating analog design lie in a general... -
ESL Design
EDA Design How-To | Engineering Articles on EDA Tools -
Business Wire
The MathWorks Expands Product Portfolio for Electronic System
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Apr
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May
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BusinessWire
45th Design Automation Conference Panels Cover Industry’s Varied -
SCDsource
Nusym promises high coverage with 'intelligent verification' -
Solid State Technology
Mentor Graphics + Ponte: "End of the DFM dream"
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June
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SCD Source
How TI copes with IC design complexity -
The Earth Times
DAFCA and Denali Software Announce Collaboration to Expand FlashPoint Platform Integration Features -
SCDsource
IEEE 'e' language update shows continuing momentum -
SCDsource
SpringSoft acquisitions build new global EDA vendor -
SCDsource - News Bytes
John Cooley has published his annual "must see list" -
SCDsource
Ten top technology developments to see at DAC -
DAC News
DAC: Around EDA in Six Days -
EETimes
Video: Gary Smith talks EDA at DAC -
Duolog Technologies
Duolog Technologies Pioneers I/O Fabric Generator for Complex SoC Designs -
EETimes
TSMC's 32-nm DFM model aims to unify design flow -
IT Business Net
Duolog Technologies Pioneers I/O Fabric Generator for Complex SoC Designs -
SCD Source
Panelists give ESL signoff a reality check -
EETimes
Group's "interoperable" analog flow turns up heat on Cadence -
EETimes Europe
EDA still software-challenged -
EETimes
Multithreading threatens to unravel beyond 45 nm -
EDACafe
DAC 2008 Trepidation to Triumph -
electronic design
Editorial Video from DAC -
EETimes
Analyst: Cadence/Mentor merger "a bad idea" -
EDA Consortium
Full Disclosure Blues Band -
SCD Source
Cadence's Mentor takeover bid challenges EDA industry -
EETimes Asia
IPL Alliance's 'interoperable' ref flow puts pressure on Cadence -
EETimes
Mentor says Cadence offer too low -
San Jose Mercury News
Cadence Goes Public With Mentor Bid -
EDN
Cadence stalks Mentor: a possible explanation -
Electronic News
EDA leader Cadence wants to buy Mentor for $1.6B -
EE Times
Is Mentor's Rhines too nice for takeover battle? -
EE Times
Mentor bid: There will be blood -
EE Times India
IPL alliance creates buzz on analogue design -
EE Times India
Cadence's CEO Fister: Driven by ambition -
EE Times India
Will Mentor fight the offer of Cadence -
Dataweek South Africa
Altium tops poll of best PCB layout tools -
SCD Source
Ciranova offers automated analog placement -
SCD Source
Gary Smith dispels EDA "fear, uncertainty, doubt" -
SCD Source
How TI copes with IC design complexity
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July
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New Electronics
In Good Shape -
SCD Source
Cadence claims 'next generation' high-level synthesis -
EDA Cafe
The Summer of Our Discontent: War Games in EDA
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Aug
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EE Times India
Magma faces tough market conditions -
EDN
Electronic-system-level design: Is there fire beneath the smoke? -
Techon NIKKEI
Gary Smith Review -
EDN
Electronic-system-level design: Is there fire beneath the smoke? -
IC Design & Verification Journal
A New Analog Golden Age?
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Sept
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EDA DesignLine
Magma: a mirror on EDA -
EE Times India
Synopsys officially enters analog/mixed-signal EDA market -
EE Times
Magma: a mirror on EDA -
EE Times India
Magma faces tough market conditions
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Oct
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EE Times Europe
Comment: Is Fister's resignation a pain or relief? -
Digital Daily
Cadence Leadership Released into Wild -
EE Times
Analysis: With Fister gone, Cadence layoff may be next -
The Street
Cadence Design Looks to Rebuild Leadership
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Nov
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Embedded.com
Software as a service in EDA:Part 2 -
EE Times India
Fister's resignation: Pain or relief?
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Dec
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EE Times
Analysis: Did Cadence hit rock bottom? -
Deepchip
With Gary Smith's warning, what should replace SoC Encounter? -
ChipDesignMag.com
The ESL Conundrum -
EE Times
Analyst sees minimal EDA growth in '09
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DV Con Panel: Where Does
Wed Feb 27, 2013 8:30-10:00
Design End & Vrfcn Begin?
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Chip Design
Industry Rethinks RTL Synthesis -
Science Web Hosting Geeks
Menadžment Dizajna & Studija Ponovne upotrebe IP -
NewTechPress
Gary Smith considers the quest for the $10K chip -
Market Watch
Atrenta Number Two in RTL Power Analysis According to Gary Smith EDA -
ARMdevices.net
Video: Gary Smith EDA’s impressions on ARM Techcon 2012
