Gary Smith EDA Consulting in Electronic Design

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Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.

2009 Archives

• Jan

  • Earth Times

    Apache Design Solutions Closes 2009 with Record Quarter and Record Year

  • EE Times - Taiwan

    Gary Smith EDA

  • Semiconducter International - China

    Gary Smith EDA

  • EE Times

    Cut some product lines?

  • EE Times

    Analysis: Cadence board puts faith in one of its own

  • EE Times Asia

    How will Tan lead Cadence's resurgence?

  • EE Times India

    Analyst: EDA market improvement in Q3

  • MarketWatc

    Solido Design Automation Launches Industry's First Extensible Process Variation Solution for Transistor-Level Designers

  • Ad-Hoc-News

    Solido Design Automation Launches Industry's First Extensible Process Variation Solution for Transistor-Level Designers

  • SYS-CON Medi

    Solido Design Automation Launches Industry’s First Extensible Process Variation Solution for Transistor-Level Designers

  
  

• Feb

  • EE Times

    ESL: Where are we and where are we going?

  • EarthTimes

    Synopsys Defines Next Era of Rapid Prototyping

  • Design and Reuse

    Synopsys Defines Next Era of Rapid Prototyping

  • EEPW

    Synopsys

  • Solid State Technology

    EDA emerging from worst year in recent history

  • Sina

    Rapid Prototyping Platform

  • EDA Cafe

    "Make or Break Year with Inflection Point" Video

  • The Earth Times

    SpringSoft Agees to Acquire Certess

  • The Earth Times

    Azuro Launches Rubix™ Clock Concurrent Optimization Tool

  • TMCnet

    Azuro Intros New Clock Concurrent Optimization Tool

  
  

• Mar

  • Chip Design Magazine

    Synthesis Needs to Change to Serve Modern Chip Design

  • EDN

    Internal development

  • DAC

    How Will ESL Change the EDA Industry?

  • The Economic Times

    Gary Smith covered in Economic Times

  
  

• Apr

  • Cadence

    Whatever Happened to Statistical Timing?

  • Cadence

    Porting EDA Applications To Multicore -- Part 1

  • EDN

    ESL and software signoff

  • EDN

    EDP 2009: Gary Smith on the State of EDA—Tumult and the Return of the ASIC Business

  
  

• May

  • TMCnet

    DAC Program Cover to Wide Range of Issues Affecting Chip Design, Technology, Business

  • Yahoo! Finance

    29 Panel Sessions in 46th Design Automation Conference Program Cover Wide Range of Issues Affecting Chip Design, Technology, Business

  
  

• June

  • SCD Source

    Mixing Formal and Dynamic Verification Part 1

  • Cadence

    Porting EDA Applications To Multicore -- Part 1

  • Cadence

    Whatever Happened to Statistical Timing?

  • Yahoo! Finance

    29 Panel Sessions in 46th Design Automation Conference Program Cover Wide Range of Issues Affecting Chip Design, Technology, Business

  • TMCnet

    DAC Program Cover to Wide Range of Issues Affecting Chip Design, Technology, Business

  • Chip Design Magazine

    Synthesis Needs to Change to Serve Modern Chip Design

  • Earth Times

    Synfora Expands Sales Team to Address Escalating ESL Market

  • Yahoo! Finance

    Synopsys Enables System Design Interoperability With System-Level Catalyst Program

  • Cadence

    Intel's Wind River Acquisition - New Help For Multicore SoCs?

  • Solid State Technology

    Cadence cutting back on the "M" in DFM

  • Shrinking Violence Blog

    Cadence about to discover why interoperability is good

  • Gabe on EDA

    Cadence's decision to leave the DFM market (or not)

  • Gabe on EDA

    Cadence Insider Speaks in Support of DFM

  
  

• July

  • EE Times

    Forte beefs up high-level synthesis tool

  • Electronic Design

    Virtualization Innovations Drive Cost Optimization

  
  

• Aug

  • Computing Now

    High-Level Synthesis: Past, Present, and Future

  
  

• Sept

  • EE Times

    Forte acquires IP, datapath synthesis vendor

  • DAC

    Gary Smith EDA wins 46DAC Best Pavilion Panel

  • EETimes UK

    Commentary: ESL may be coming into its own

  • Gabe on EDA

    Mentor Graphics Launches Precise-IP

  • Business Wire

    Mentor Graphics Launches Precise-IP Vendor-Independent IP Platform for FPGA Design

  
  

• Oct

  • System-Level Design

    The FPGA Alternative

  • AjaxWorld Magazine

    Silicon Frontline Announces Success and Recognition; Post-Layout Verification Products Stand Out for Semiconductor Power

  
  

• Nov

  • EE Times

    Saas and EDA: Are designers ready?

  • Mentor Graphics Blogs

    SystemC, Ten Years Later…

  • EDA Cafe

    Gary Smith EDA Reports EVE Leads Design Team Acceleration, Emulation Market

  • Chip Design Magazine

    When It Comes To Intellectual Property, Size Matters

  • EE Herald

    Silicon Frontline's post-layout verification tool is validated by UMC and TSMC

  • Chip Design Magazine

    Hypervisors For Managing Power

  • Chip Design Magazine

    Power Trip Advisor

  • Mentor Graphics Blogs

    Gary Smith’s ESL 2009 Market Trends

  • Chip Design Magazine

    NoCs Move Downstream

  • SCD Source

    Randal Bryant receives the 2009 Phil Kaufman Award

  
  

• Dec

  • EarthTimes

    Open SystemC Initiative Commemorates 10-Year Anniversary of Service to System-Level Design Community

  • DeepChip

    Cooley's DAC report: Mentor Olympus-Calibre and AtopTech Aprisia

  • DeepChip

    Cooley's DAC report: Forte Cynthesizer, Calypto SLEC, AutoESL

  
  

• Events

  • DAC

    Mon July 27 2009 10:45am-11:45am

    EDA Heritage Series: Doug Fairbairn's Industry Retrospective Booth #1928

  • DAC - Gary Unplugged

    Tues July 28 2009 4:45pm

    Killer Apps for the Next Decade AutoESL Booth 3755

  • DAC

    Sun July 26 2009 5:30 -7:30 pm

    Welcome Night Reception Intercontinental SF Hotel Grand Ballroom

  • DAC 2009

    Mon July 27 2009 9:30am-10:30am

    Gary Smith on EDA: Trends and What is Hot at DAC Booth #1928